Parameter optimization of a Josephson latching driver based on bit-error-rate simulations

Abstract

We have calculated a bit-error-rate (BER) of Josephson latching drivers using the Monte-Carlo simulations taking into account the thermal noise at the Josephson junctions. The latching driver under investigation is composed of parallel 8-junction stacks and a SQUID input gate. We have optimized the structure of the SQUID input gate based on the BER simulation to get larger bias margins with acceptable BER.We have shown that the bias margins of the latching driver with a 3-junction SQUID input gate are better than that using a 2-junction SQUID input gate. The high-speed measurement of the Josephson latching driver confirms the validity of the BER based optimization. We have obtained the BER lower than 10−12 at 5GHz and 10−5 at 10GHz in the Josephson latching driver with the 3-junction SQUID input gate by the high-speed test.