Abstract
j-lanes tree hashing is a tree mode that splits an input message into j slices, computes j independent digests of each slice, and outputs the hash value of their concatenation. j-pointers tree hashing is a similar tree mode that receives, as input, j pointers to j messages (or slices of a single message), computes their digests and outputs the hash value of their concatenation. Such modes expose parallelization opportunities in a hashing process that is otherwise serial by nature. As a result, they have a performance advantage on modern processor architectures. This paper provides precise specifications for these hashing modes, proposes appropriate IVs, and demonstrates their performance on the latest processors. Our hope is that it would be useful for standardization of these modes.
Highlights
This paper expands upon the j-lanes tree hashing mode which was proposed in [1]
The specification is general, we focus on j-lanes tree hashing with SHA-256 [2] as the underlying hash function
The j-lanes mode is a particular form of tree hashing, which is optimized for contemporary architectures of
Summary
This paper expands upon the j-lanes tree hashing mode which was proposed in [1]. It provides specifications, enhancements, and an updated performance analysis. (2014) Parallelized Hashing via j-Lanes and j-Pointers Tree Modes, with Applications to SHA-256. The AVX2 architecture [3] includes all the necessary instructions to implement SHA-256 operations efficiently: 32-bit shift (vpsrld) and add (vpaddd), bitwise logical operations (vpandn, vpand, vpxor), and the 32-bit rotation (by combining two shifts (vpsrld/vpslld) with a single xor/or (vpxor) operation). The future AVX512f instructions set [3] [5] supports 512-bit registers, ready for operating on 16 lanes It adds a few useful instructions that would increase the parallelized hashing performance: rotation (vprold) and ternary-logic operation (vpternlogd). Rotation (vprold) can perform the SHA-256 rotations faster than the vpsrld + vpslld + vpxor combination
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