Parallelized and pipelined hardware implementation of computationally expensive prediction filters

Abstract

AbstractIn this paper parallelization and segmentation methodologies are used to obtain a real‐time (RT) implementation of computationally expensive estimators or filters in an FPGA. First, the filter to be applied is briefly described, and afterwards its hardware structure and VHDL implementation are indicated. A comparative study is performed between the FPGA parallelized implementation and the implementation in a sequential processor. The analysis proves that the execution times measured on the FPGA are considerably lower, making that implementation valid for its use in RT systems. Moreover, several experimental results are shown for a visual servoing application in order to evidence the good performance of the proposed algorithms and implementations. Copyright © 2009 John Wiley & Sons, Ltd.