Abstract

Space mapping (SM) methodology has been recognized as a powerful tool for accelerating electromagnetic (EM)-based yield optimization. This paper proposes a novel parallel space-mapping based yield-driven EM optimization technique incorporating trust region algorithm and polynomial chaos expansion (PCE). In this technique, a novel trust region algorithm is proposed to increase the robustness of the SM surrogate in each iteration during yield optimization. The proposed algorithm updates the trust radius of each design parameter based on the effectiveness of minimizing the l 1 objective function using the surrogate, thereby increasing the robustness of the SM surrogate. Moreover, for the first time, parallel computation method is incorporated into SM-based yield-driven design to accelerate the overall yield optimization process of microwave structures. The use of parallel computation allows the surrogate developed in the proposed technique to be valid in a larger neighborhood than that in standard SM, consequently increasing the speed of finding the optimal yield solution in SM-based yield-driven design. Lastly, the PCE approach is incorporated into the proposed technique to further speed up yield verification on the fine model. Compared with the standard SM-based yield optimization technique with sequential computation, the proposed technique achieves a higher yield increase with shorter CPU time by reducing the number of SM iterations. The proposed technique is illustrated by two microwave examples.

Highlights

  • Yield optimization, called design centering, is an optimization process that aims to find a nominal design solution with the maximum yield [1]

  • We explore the possibility of combining Space mapping (SM) and polynomial chaos expansion (PCE) to solve the EM-based yield optimization problem

  • This paper proposes a novel parallel space-mapping based yield-driven EM optimization technique incorporating trust region algorithm and PCE

Read more

Summary

INTRODUCTION

Called design centering, is an optimization process that aims to find a nominal design solution with the maximum yield [1]. This paper proposes a novel parallel space-mapping based yield-driven EM optimization technique incorporating trust region algorithm and PCE. PROPOSED PARALLEL SPACE-MAPPING BASED YIELD OPTIMIZATION TECHNIQUE INCORPORATING TRUST REGION ALGORITHM AND PCE A direct application of the objective function U (x0) is feasible if the responses are computed by circuit simulations. In this paper, for the first time, we propose a parallel SM based yield-driven EM optimization technique incorporating trust region algorithm and PCE. The proposed technique mainly consists of five parts, namely, fine model data generation with parallel computational method, surrogate modeling over multiple geometrical samples with parallel computation method, the l1 design centering algorithm to optimize the yield using the surrogate model, a novel trust region algorithm to update the trust region of the surrogate, and the PCE approach to yield verification on the fine model. We provide the descriptions for these five parts in the subsequent sections

FINE MODEL DATA GENERATION WITH PARALLEL COMPUTATION METHOD
PROPOSED TRUST REGION ALGORITHM FOR PARALLEL SM BASED YIELD OPTIMIZATION
INCORPORATING THE PCE APPROACH FOR YIELD VERIFICATION ON THE FINE MODEL
THE PROPOSED YIELD OPTIMIZATION ALGORITHM
YIELD OPTIMIZATION OF A BANDSTOP MICROSTRIP FILTER WITH OPEN STUBS
Findings
CONCLUSION
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call