Parallel Simulation of Digital Logic Circuits Using Message Passing via CSP as an Educational Tool

Abstract

The present work shows an educational application of practical utility for the learning of the Parallel and Concurrent Programming with passage of messages, through the simulation of the digital logical circuits, as an excellent example of the inherent parallelism in the behavior of this type of systems. The Java class library called JPMI is used, which provides the base classes to generate processes, channels and composition of processes: sequential, parallel and alternative; for the parallel implementation of the most useful gates in the area of digital systems such as, the AND, OR and NOT gates. It shows a basic case study of the use of the JPMI library for the parallel implementation of a simple digital logic circuit and with this implementation simulate its logical behavior. But the full implementation of a 4-bit digital logic counter as an educational application or simulator is also shown. The objective of this work is, on the one hand, to demonstrate that the proposed implementations help the student through the simulation to understand and learn both the construction and the functioning of the digital systems, and on the other hand to show the inherent relationship of the parallelism with the operation of these systems.