Abstract
Based on the adders with a minimum number of NOR gates discussed in Ref. 1, parallel multiplers are designed in Ref. 2, using fewer gates, fewer connections, and faster operation than conventional multipliers based on carry-save adders. In this paper, parallel multipliers of NOR gates are designed, by expressing two numbers to be multiplied in the sign and magnitude representation unlike those in Ref. 2. The multipliers in this paper are advantageous over the carry-save adder-type multipliers known to date, in terms of the number of gates and connections.
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