Abstract
The memory requirements of turbo decoders are high since long code block lengths are preferred. Especially, the extrinsic information memory is accessed frequently with both linear and interleaved access patterns. In this paper, a parallel access scheme into extrinsic information memory is developed for a 3GPP turbo decoder. A single port memory is divided into parallel accessible modules and the memory throughput requirements and both the linear and interleaved access patterns are considered as module and word address generating functions are developed. As a result, the throughput of the parallel access scheme allows high-speed decoding and the usage of the dual port memory can be avoided and savings in chip area are achieved.
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