Parallel implementation of hardware-efficient adaptive equalization for coherent PON systems

Abstract

The development of the fifth generation mobile (5G) technique stimulates a higher bandwidth requirement for next generation passive optical network (PON) systems. It is a challenge to further double the data rate from 50 to 100 Gb/s/λ depending on intensity modulation direct detection due to stringent bandwidth constraints on optical and electrical components. Coherent detection technology is a promising candidate for the future 100 Gb/s/λ or higher PON systems. The parallel implementation of hardware-efficient adaptive equalization tailored to PON systems will accelerate the evolution of coherent PON systems. In view of the current situation that logic resources are abundant while hardened multipliers are few for commercial field programmable gate array (FPGA), the purpose of this work is to reduce the number of hardened multiplexers used for FPGA realized signal processing. The waveform distortion caused by chromatic dispersion (CD) and imperfect frequency response of transceiver is rough compensated by using frequency domain equalization, which alleviate the stringent filter length requirement for the following adaptive equalization. Three Coordinate Rotation Digital Computer-based vector rotators are introduced to realize polarization demultiplexing, where the state of polarization is tracing by using a simplified gradient descent algorithm. A non-butterfly equalizer with few taps for each polarization is designed to handle the residual (CD) and the frequency response difference due to external environment variations and manufacturing technology. With the proposed method, the number of hardened multipliers is reduced by 73% compared with conventional 2×2 multiple-input multiple-output equalizer under the case with the similar receiver sensitivity.