Parallel image processing field programmable gate array for real time image processing system

Abstract

A parallel images processing field programmable gate array (FPGA) for real time image processing system has been proposed to realize high image processing speed and flexibility. This FPGA has a small size configuration memory. In addition, a parallel reconfigurable interconnection network and logic blocks have been used in this FPGA. A test chip was designed and fabricated using 0.35 /spl mu/m CMOS technology. It was confirmed in the test chip that the reconfiguration of the image processing is successfully performed.