Parallel Concatenated Block Codes Constructed by Convolutional Interleavers

Sina Vafi

doi:10.1109/access.2021.3065236

Abstract

This paper presents the application of convolutional interleavers for constructing high performance parallel concatenated block (PCB) codes. The utilized interleaver is operated as a block interleaver, when the number of stuff bits is applied at the first and end parts of the interleaving. A modification is conducted to reduce the number of stuff bits and ensure that every block of the interleaved data has at least one stuff bit. Conducted simulations confirm that with the similar code length and rate, the newly proposed codes have close or better performance than other well-known codes recommended for the global telecommunications standards.

Highlights

T HE main aim of emerging broadband transmission systems is the reliable delivery of the information from the source to the destination [1] [2] [3]
This paper presents a new scheme of convolutional interleavers, which satisfy the abovementioned condition for parallel concatenated block (PCB) codes
SIMULATION RESULTS Performance of different PCB codes based on convolutional interleavers proposed in Section III is verified by the number of simulations

Summary

INTRODUCTION

T HE main aim of emerging broadband transmission systems is the reliable delivery of the information from the source to the destination [1] [2] [3]. The proposed code applies the main specifications of constituent codes in the correction of errors as well as parallel encoding and decoding facilities of LDPC codes aiming to minimize the design complexity [7]. The performance of PCB codes can be improved by an interleaver, whose length is greater than the length of the message This can be achieved by utilizing convolutional interleavers, which add number of bits to the rearranged message. Similar to the convolutional interleavers applied for turbo codes, the structure of the proposed interleaver is optimized by reducing the number of stuff bits [15] Another modification is accomplished to ensure that inserted stuff bits are properly distributed so as every interleaved message has at least one stuff bit.

STRUCTURE OF PCB CODES

ERROR CORRECTING CAPABILITY OF PROPOSED PCB CODES

ANALYSIS OF ITERATIVE DECODING FOR PCB CODES

DECODING COMPLEXITY OF THE CONSTRUCTED PCB CODE

VIII. CONCLUSIONS AND FUTURE WORK