Parallel Computations and Delay-Insensitive Circuits

Abstract

Delay-insensitive circuits are attractive implementations for parallel computations. A delay-insensitive circuit is a special type of asynchronous circuit and can informally be characterised as a network of components of which the correctness is insensitive to delays in basic components and connection wires. The principles underlying the design of delay-insensitive circuits are explained. By means of a few examples we illustrate how parallel computations can be expressed conveniently in a simple program notation. In particular the design of the proper synchronisation among the subcomputations is illustrated. Subsequently, we show how such a program can be transformed into a delay-insensitive circuit and how timing problems can be avoided in implementing the synchronisations.