Abstract
The sophistication of applications and hunger for high quality digital data demands increase in the processing power. High performance signal processing is possible only though parallelism. At the same time, flexibility and scalability are the need of the hour due to dynamically changing standards and design up gradation. This paper describes an implementation of the computational framework using the DSP Slices in the FPGA. The customized instructions will provide the computation flexibility whereas specialized DSP macros in FPGA ensure high performance.
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