Parallel channel interleavers for 3GPP2/UMB

Abstract

The design of efficient parallel pruned channel interleavers for 3GPP2 ultra mobile broadband (UMB) standard is considered. Channel interleaving in UMB is based on a bit-reversal algorithm in which addresses get mapped from linear order into bit-reversed order. To accommodate for variable packet lengths L, interleaving is done using a mother interleaver length of M = 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> , where n is the smallest integer that satisfies L les M, such that outlier interleaved addresses greater than L-1 get pruned away. Pruning creates a serial bottleneck since the interleaved address of a linear address x is now a function of the interleaving operation as well as the number of pruned addresses up to x. A generic parallel lookahead pruned (PLP) interleaving scheme that breaks this dependency is proposed. The efficiency of the proposed scheme is demonstrated in the context of UMB channel interleavers in this paper, and in the context of UMB turbo interleavers in a separate work . An iterative pruned bit-reversal algorithm that interleaves any address in O(log L) steps is presented. A parallel architecture of the proposed algorithm employing simple logic gates and having a short critical path delay is also presented. The proposed algorithm and architecture are valuable in reducing (de-)interleaving latency in emerging wireless standards that employ pruned bit-reversal channel (de-)interleaving in their PHY layer such as UMB.