Parallel architectures for programmable high-speed signal processing devices

Abstract

For programmable high-speed digital signal processing devices the proper architecture has to be carefully selected according to the algorithms to be implemented. The appropriate number of arithmetic units depends on the degree of parallelism of the signal processing algorithm. The question of parallelism of algorithms is discussed. For the efficient exploitation of a given signal processor hardware, an appropriate processor schedule is necessary. In two examples different approaches for multiprocessor architectures are discussed. >