Abstract
The paper describes a novel implementation of the modified Booth algorithm in which groups of the partial product terms are summed in parallel and these partial results are then combined in a Wallace tree adder array. The final output is formed by an accelerated carry adder. An extension of the scheme from unsigned binary arithmetic to 2's complement is also described. A 16-bit version of the architecture has been modelled in Pascal and Ella to validate its operation for use in a systolic array DSP chip.
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