Parallel Algorithms with Processor Failures and Delays

Abstract

We study efficient deterministic parallel algorithms on two models: restartable fail-stop CRCW PRAMs and asynchronous PRAMs. In the first model, synchronous processes are subject to arbitrary stop failures and restarts determined by an on-line adversary and involving loss of private but not shared memory; the complexity measures arecompleted work(where processors are charged for completed fixed-size update cycles) andoverhead ratio(completed work amortized over necessary work and failures). In the second model, the result of the computation is a serialization of the actions of the processors determined by an on-line adversary; the complexity measure istotal work(number of steps taken by all processors). Despite their differences, the two models share key algorithmic techniques. We present new algorithms for theWrite-Allproblem (in whichPprocessors write ones into an array of sizeN) for the two models. These algorithms can be used to implement a simulation strategy for anyNprocessor PRAM on a restartable fail-stopPprocessor CRCW PRAM such that it guarantees a terminating execution of each simulatedNprocessor step, withO(log2N) overhead ratio, andO(min{N+Plog2N+MlogN,N·P0.59}) (subquadratic) completed work (whereMis the number of failures during this step's simulation). This strategy has a range of optimality. We also show that theWrite-AllrequiresN+Ω(PlogP) completed/total work on these models forP≤N.