PAM-4 implementation study for future high-speed links

Abstract

With the ever-increasing amount of data produced by the high energy physics experiments, the transmission rates from the detectors to the back-end stages must keep up. To mitigate the exponential growth of the total loss due to the increased bandwidth, the 4-Level Pulse-Amplitude Modulation (PAM4) could be envisaged. Where the line rate of Non-Return to Zero (NRZ) modulated signals is capping at 28 Gbps per lane, PAM4 allows the rate of 53.125 Gbps or above in extremely high-end applications. Investigating the implementation of such links in FPGA is one of the activities carried out by the Work Package 6 of the CERN EP Research and Development programme. A proof-of-concept system of high-speed links using PAM4-53.125 Gbps has been built, based on a Xilinx Virtex evaluation platform and various commercial optoelectronics transceivers. PAM4 standard Forward Error Correction (FEC) codes have also been implemented and characterized over electrical and optical layers in terms of coding gain and latency. Finally, the telecom and datacom markets were investigated to identify development perspectives for the research and development for future links. In this paper, the performance of the proof-of-concept implementing these high-speed links is presented and the current and future challenges for an error-free communication are discussed.