Packing Narrow-Width Operands to Improve Energy Efficiency of General-Purpose GPU Computing

Abstract

In this paper, we study the use of OWAR, an_Qperand-Width-A_ware Register packing mechanism for GPU energy saving. In order to efficiently use the GPU register file (RF), OWAR employs a power gating method to shut down unused register sub-arrays for reducing dynamic and leakage energy consumption of RF. As the number of register accesses is reduced due to the packing of the narrow width operands, the dynamic energy dissipation is further decreased. Finally, with the help of RF usage optimized by register packing, OWAR allows GPUs to support more TLP (Thread Level Parallelism) through assigning additional thread blocks on SMs (Streaming Multiprocessors) for GPGPU (General-Purpose GPU) applications that suffer from the deficiency of register resources. The extra TLP opens opportunities for hiding more memory latencies and thus reduce the overall execution time, which can lower the overall energy consumption. We evaluate OWAR using a set of representative GPU benchmarks. The experimental results show that compared to the baseline without optimization, OWAR can reduce the GPGPU's total energy up to 29.6% and 9.5% on average. In addition, OWAR achieves performance improvement upto 1.97X and 1.18X on average.