Packaging technology and design challenges for fine pitch Cu pillar and BOT (Bond on Trace) using thermal compression bonding

Abstract

As copper (Cu) bump technology becomes more mature, it is gradually taking the place of the conventional solder base bump in flip chip interconnections. Especially, micro-bump using Cu-pillar bump has already become essential platform technology for devices requiring finer bump pitch less than 100μm down to 40∼20μm. Several motivations that Cu bump brings over solder bump are the fine pitch scaling capability in package assembly process, superiority of mechanical endurance and electrical performance. Although the baseline packaging technologies using Cu bump for around 50μm bump pitch and smaller than 100mm2 chip size has been in high volume production for many years, there are still many areas need further development to expand the technology envelop to finer pitch application and larger chip size i.e. less than 40μm multi-tier bump pads with larger than 400∼600mm2 die size. Comprehensive experimentation have been conducted to get optimum Cu pillar structure, package substrate design and the metal finish, thermal compression bonding process and the underfill method for finer pitch but larger chip size packaging. This paper will discuss about the technical findings and recommendation based on the lessons learned from the series of experimentation, experience from high volume production in both component manufacturing and board level surface mounting, including remaining challenges for achieving larger scale high density chip-on-substrate application in future.