Packaging and Interconnect Considerations in Neuromorphic Photonic Accelerators

Abstract

Developing compute platforms capable of performing computations at high speed is essential for data processing in the next generation of data centers and edge devices. A neuromorphic photonic accelerator on a silicon photonic platform is a promising solution. Compared to silicon photonic data communication transceiver modules, neuromorphic photonic accelerators constitute a large number of active and passive components and optoelectronic devices to handle the parallel processing. Thus, an increased number of optical and electrical interconnects are required, making the packaging of such processors challenging. Moreover, thermal and electrical crosstalk can dramatically degrade the performance of such processors. Thus, packaging a neuromorphic photonic accelerator for efficient processing and data movement requires careful considerations at the chip, module, and board levels. This work investigates the challenges and potential solutions for optical coupling, optical and electrical interconnections, processor-memory communication, and thermal and electrical cross-talk to develop neuromorphic photonic accelerators.