Abstract
Two, 36-pin, chip-carrier packages are reported which meet the requirements of ultra-high-speed GaAs ICs with up to 3GHz clock rates and 100 picoseconds rise and fall times. The packaging requirements are analyzed on the basis of propagation delay, stub lengths, cross-talk and power supply regulation. Tw packages with internal groundplane, power-supply by-pass capacitors and a maximum package dimensions of 1cm×1cm are developed. The first packaging approach is based on a multilayer co-fired ceramic technology, whereas, the second approach utilizes a silicon IC as a chip-carrier upon which the GaAs IC die is mounted. In the later case the Si-chip provides shielded transmission lines, power supply regulation, terminating and damping resistors as well as lowers the thermal resistance of the package.
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