Abstract
AbstractA Receiver incorporating bang‐bang (binary) CDR for high speed intra panel interface is proposed. The proposed Receiver adopting Phase Locked Loop (PLL) based CDR provides high speed data rate by a bang‐bang Phase Detector and Current Mode Logic (CML). Also it provides low EMI for LCD system by embedding the clock signal without explicit clock lines and scrambling active data. The results are validated on a 55‐inch full‐HD (1920×1080) TFT‐LCD panel with the 8‐bit RGB and 120Hz driving technology. Maximum data rate is measured as higher than 2.4Gbps.
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