Abstract
In this paper, one of goals is to elucidate Vt behaviors of a top gate LTPS‐TFT fabricated on the PI substrate exposed to the negative bias temperature stress (NBTS), hot carrier injection (HCI) and breakdown voltage (BV). Physical and device characterization intend to comprehend the structural dependency of LTPS‐TFT on Vt stability and reliability in comparison to the glass substrate. It is found that turn‐over Vt behaviors of a top gate LTPS‐TFT on the polyimide (PI) substrate depends on negative bias temperature stress (NBTS) conditions. Vt behaviors are attributed to LTPS‐TFT structure dependent intrinsic negative charges at the interface between the barrier and PI substrate, causing the accumulation of positive charges at the poly‐Si back channel. In fact, intrinsic process parameters, such as barrier thickness and PI cure conditions, play important roles to control interfacial charges at the interface. Finally, streamlined barrier process enables LTPS‐TFT on PI substrate to expand advanced flexible applications without compromising luminescence and reliability.
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