P/sup 2/EDAS: asynchronous, distributed event driven simulation algorithm with inconsistent event preemption for accurate execution of VHDL descriptions on parallel processors

Abstract

The DoD's very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype. Since its conception in the early 1980s, an important goal of VHDL has been to execute complex models concurrently and efficiently on parallel processors. To achieve this objective while exploiting the maximum theoretical parallelism, one requires a deadlock-free, asynchronous, distributed, discrete event simulation algorithm. The YADDES approach, proposed in the literature, achieves deadlock-free, distributed, discrete event simulation, but suffers from an important limitation. YADDES assumes that every entity is characterized by a single propagation delay. In contrast, for hardware entities such as gates, flip-flops, ALUs, and microprocessors, two or more propagation delay values are used corresponding to every path between the input and output. While the use of multiple delays aims at accurate representation of reality, often inconsistent events may be generated that must be detected and preempted. This paper describes a new asynchronous, parallel, event driven simulation algorithm with inconsistent event preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in that it permits the use of any number of propagation delays for every path between the input and output of every hardware entity.