P heterostructure field effect transistors

Abstract

We propose a new Heterostructure Field Effect Transistor (HFET) structure. The proposed device is a quantum-well HFET with a p+ gate and fairly heavily doped p-type buffer. We call this device a TC-HFET meaning p-type Insulated gate HFET. The effective barrier height in a TC-HFET is considerably larger than in other compound semiconductor FETs and the gate current and real space transfer problem at maximum gate voltage swing can be made negligible even at room temperature. Based on the trade-off between the noise margin and speed, we propose 0.7 V and 1.5 V as the minimum power supply voltages for the direct coupled FET logic at 77 and 300 K, respectively. Our calculations demonstrate that this TC- HFET technology can meet all requirements for VLSI applications and that high electron velocity and mobility in TC-HFETS lead to an increase in speed of output drivers by a factor of four at 77 K and a factor of 10 at 300 K (compared to Si NMOS which is faster than CMOS). The full advantages of TC-HFET technology can be only realized on a submicron scale where source and drain series resistances play a dominant role in determining the noise margin. This leads to the necessity to modify both the device design and fabrication process for better control of series resistance uniformity. In order to reduce the series resistances, we propose new self-aligned fabrication processes for TC-HFETS such as a modified SAINT process and a modified T-gate process.