P‐6.11: ESD Related Defects Analysis and Improvement Design Solution in TFT‐LCD Array Process

Abstract

In this paper, the question of point defects caused by ESD (electrostatic discharge) is analyzed, and the method of reducing ESD risk is proved via unconventional pixel ITO (indium tin oxide) design. Through the analysis of the actual verification results, it is found that the phenomenon of ESD occurs between the dry etching of the channel and the SiNx (silicon nitride) film formation of passivation. The results also show that the occurrence of ESD point defects is related to product design. Compared with the products designed based on metal com and mid com, the products designed based on top com are more prone to ESD point defects. The ESD defect ratio increases with the increase of pixel ITO area in the top com and mid com products. In order to reduce the ESD defect ratio, the pixel ITO of top com products can be designed to partially cover the gate line, which refers to the design of metal com. In the experiment, the ESD defect ratio of 7‐inch top com product with the unconventional ITO design is reduced from 1.59% to 0. The results fully demonstrate that unconventional pixel ITO design can be applied to the actual product to reduce the ESD risk during the array process.