P‐6.1: Asymmetric Effects of Gate‐Bias Stress Voltage on the Stability under Positive and Negative Gate‐Bias Stress of a‐IGZO TFTs

Abstract

The asymmetric effects of gate‐bias stress voltage on the stability under positive gate‐bias stress (PBS) and negative gate‐bias stress (NBS) of amorphous InGaZnO thin‐film transistors (a‐IGZO TFTs) are investigated. It is observed that under PBS, the threshold voltage shift (∆Vth) increases with the increased value of the gate‐bias stress voltage (VStress), which is due to the enhanced electron trapping at/near the interface of the channel and the gate insulator. However, under NBS, the ∆Vth is nearly unaffected by the Vstress. As the NBS‐induced negative ∆V th is resulted from electron‐detrapping from the donor‐like states related to oxygen vacancies, it is supposed that the rate of electron‐detrapping is not sensitive to the negative gate‐bias voltage. The influence of N2O plasma back‐channel treatment is also studied. The stability under NBS is effectively improved after the N2O plasma treatment, which originates from the decreased density of oxygen‐vacancy related donor‐like states within the a‐IGZO channel layer.