P‐12: Transient Drain Current Characteristics of Poly‐Silicon TFTs on Plastic Substrates

Abstract

The mechanism and improvement of transient drain current characteristics of p‐channel low‐temperature polycrystalline silicon driving‐thin film transistor (LTPS DTFT) were studied in this work. The drain current variation with time can be simulated by attenuation of logarithmic index which might be originated from hole trapping and de‐trapping process. Simulation was used to directly correlate the transient Ids characteristics to the density of border trap. We optimized the buffer and gate insulator layer deposition condition, in addition, we applied a fixed bias in TFT bottom gate, the transient Ids decreased from 27% to 15%.