P‐1.6: Effect of Deposition Condition of Passivation Layer on the Performance of Self‐Aligned Top‐Gate a‐IGZO TFTs

Abstract

In this paper, we fabricated self‐aligned top‐gate (SATG) amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs). The conductive source/drain regions were formed by hydrogen incorporation during the deposition of SiOx or SiNx passivation layer using plasma‐enhanced chemical vapor deposition (PECVD). The effect of passivation layer deposition condition on the electrical performance of self‐aligned top‐gate a‐IGZO TFTs was investigated. It was shown that the source‐drain parasitic resistance (Rsd) was effectively reduced during the deposition of SiNx passivation layer than SiOx. However, as the deposition temperature of SiNx passivation layer increased, hydrogen lateral diffusion into channel region resulted in the shrinkage of effective channel length and the deterioration of electrical performance of short‐channel device.