Abstract
AbstractSynchrotron section topography is applied to the study of silicon wafers pulled out froma simulated advanced CMOS twin-tub process. Substrates are heavily doped with antimony and phosphorus. For comparison also high-resistivity samples are studied. Prior to epi deposition of arsenic doped layers some wafers are subjected to a three-step intrinsic gettering cycle.Section topographs show that in the lightly doped samples a denuded zone is formed by the CMOS process itself in contrast with the heavily doped ones in which the intrinsic gettering is needed.
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