Abstract
Describes the use of selective oxidation and ion implantation to fabricate integrated circuits. The technique of selective oxidation is used to fabricate a `walled emitter' structure as proposed by Panousis. This allows a substantial reduction in transistor size, for a given active area, over standard fabrication techniques. At the same time, parasitic device capacitances are reduced and a considerable improvement in circuit performance is realized. The impurity distribution in the various components is established by the extensive use of ion implantation. It has been demonstrated, experimentally, a 30-pJ resistor transistor-transistor logic gate fabricated using the collector diffusion isolation technology, can be fabricated in oxide isolated monolithic technology with a power-delay product of 6 pJ. Current-mode logic gates have been fabricated with a power-delay product of 1 pJ.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
