Oxide Thickness‐ and Bias‐Dependence of Postmetallization Annealing of Interface States in Metal‐Oxide‐Silicon Diodes

Abstract

Fast interface states were studied in p‐type, 〈100〉 oriented, Al gate metal oxide silicon (MOS) diodes with dry grown oxides in the ∼2 to 20 nm thickness range. We show that the high frequency quasi‐static capacitance‐voltage (C‐V) method is unsuitable for characterizing states located within 0.25 eV from the valence band since those respond to a 1 MHz signal. Specially adapted C‐V methods reveal that all interface states probed across the bandgap show similar rates of passivation during unbiased postmetallization anneal (PMA) independent of the oxide thickness. For dc biased PMA the passivation of states at E‐Ev ≈ 0.25 eV, believed to comprise the lower level of Pb centers, is promoted by negative bias for all thicknesses used. A marked deviation from this behavior for states at midgap indicates that their concentration cannot be used as a generally valid measure of the Pb concentration.