OVL, PSL, SVA: Assertion based verification using checkers and standard assertion languages

Abstract

Over a number of years, assertion-based techniques have been growing in importance as part of functional verification methodologies for industrial semiconductor designs. This acceptance has given way to the use of assertion properties making verification look simpler for those verification engineers when compared to simulation based verification. To add on the standardization of industrially focused assertion languages, like System Verilog Assertions (SVA) and Property Specification Language (PSL) has occurred. Whereas Accellera Open Verification Library (OVL) standard fulfills the long-anticipated vision of creating a vendor-and languageindependent assertion library that can be used across various verification process. This paper emphasizes on how checkers (libraries) and assertion languages enhances the verification process without comprising on the quality of verification.