Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Abstract

This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasonable number of stacked memory layers (≤ 32) and thus potentially offers lower cost. VG NAND has good pitch scalability thus is very attractive. On the other hand, it is more difficult to decode the bit line in a VG architecture, thus decoding innovations are required for a compact array architecture design. This paper provides a systematic comparison of four different decoding methods of VG NAND. Performance of the TFT BE-SONOS device used in 3D VG NAND is also addressed.