Overview: continuous evolution on double-patterning process

Abstract

Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pith-Quadrupling (SAQP) achieved 11nm hp as introduced in last SPIE[1]. PR-core technique will be most friendly for lithographer, because its property can be recognized on lithography view point. ALD (Atomic Layer deposition) SiO2 process is the one of unique technique for multiple-patterning, and it is also useful for pitch-doubling in hole pattern [2]. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened. In this study, we would demonstrate newly developed multi-patterning techniques and optimize CD-uniformity, LWR and process latitude.