Overview and future developments of the FPGA-based DAQ of COMPASS

Y Bai,M Bodlak,J Novy,M Virius,D Levit,V Frolov,I Konorov,D Steffen,V Jary,S Huber

doi:10.1088/1748-0221/11/02/c02025

Abstract

COMPASS is a fixed-target experiment at the SPS at CERN dedicated to the study of hadron structure and spectroscopy. Since 2014, a hardware event builder consisting of nine custom designed FPGA-cards replaced the previous online computers increasing compactness and scalability of the DAQ. By buffering data, the system exploits the spill structure of the SPS and averages the maximum on-spill data rate over the whole SPS cycle. From 2016, a crosspoint switch connecting all involved high-speed links shall provide a fully programmable system topology and thus simplifies the compensation for hardware failure and improves load balancing.

Highlights

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The triggers are distributed by the Trigger Control System (TCS) [3] together with a reference clock and event labels to all data concentrator and event builder modules via a passive optical fiber network
The hardware event builder (EB) of the new FDAQ consists of nine custom designed DAQ units with identical PCB layout and eight-off-shelf FPGA cards, called spillbuffer cards, which are plugged into eight readout computers

Summary

Design of the hardware event builder

Due to aging of components and related loss of modules, the DAQ’s event building architecture needed a revision [8]. The hardware EB of the new FDAQ consists of nine custom designed DAQ units with identical PCB layout and eight-off-shelf FPGA cards, called spillbuffer cards, which are plugged into eight readout computers Despite their identical layout, the DAQ units are used differently in the EB, as can be seen in figure 1: eight of them are programmed with a firmware that allows to use them as 15x1-multiplexer (DHCmx), and one is programmed as 8x8-switch (DHCsw), distributing the data sent by the multiplexers to the spillbuffers in a round robin manner on event basis. As soon as the last data check logic has filled its event fragment into the memory bank, it passes the memory address and size of the event to an event reader, which reads the whole event from the DDR memory and sends it via S-Link to its corresponding spillbuffer This firmware setup requires a revision of the memory interface and provides less efficient use of the DDR3 SDRAM, but it has full throughput bandwidth of 1.6 GB/s

Software architecture

Future developments

Results and conclusion