Abstract

This paper investigates techniques to speed up HSSI bit-error rate (BER) and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). Parallel BERT elements are able to digitize the input signal jitter behavior in a multi-phase manner. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.

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