Overlay as the key to drive wafer scale 3D integration

Abstract

3D integration is the stacking of multiple active device layers (with or without interconnecting metal lines) to form a more complex integrated circuit or to provide a new architectural venue. There are many different techniques to accomplish the stacking of the active layers, ranging from packing solutions through wafer bonding, to regrowth of Silicon films. We utilized an aligned SOI wafer bonding method that allows very high alignment accuracy to achieve very dense 3D interconnections. However, wafer bonding tools currently do not have the capability to achieve better than 100 nm overlay error (3 sigma). This limits the highest density we can achieve in a 3D design due to the large landing area that is required to yield the 3D vias, reducing the areal benefit and thus worsening yields. Hence, in this work we will discuss key issues that prevent better than 100 nm 3 sigma alignment between the two substrates. We show that controlled process integration enables significant reduction of the alignment errors between two substrates. The second part of the paper details 3D bonder re-engineering solutions to achieve an order of magnitude improvement in alignment accuracy and drive the full potential of 3DIC. More specifically, inclusion of the learning achieved from lithographic technology, as well as specific bonding process control methods are discussed.