Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps

Abstract

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention. Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents the reliability results as well as micro-bump resistance data. In addition, preconditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA. Furthermore, this paper details the outstanding TSV Keep-Out-Zone study (KOZ) for an active silicon interposer and the effect of TSV stress on transistor electron and hole mobility. Finally, an advanced thermal study of TSV interposer technology is presented to cool down a high-performance 28nm logic die (thousands of micro-bumps) that is mounted on a large silicon interposer with Cu through silicon via. Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures.