Abstract
A stacked multicell converter (SMC) is an inverter specially adapted to high voltage applications. This inverter is composed of commutation cells ordered in p rows and n stacks, reducing semiconductor commutation stresses and high operation frequencies can be reached. This structure requires 2(pxn) switches to generate an output signal similar to a sinusoidal waveform. However, the switches must be correctly controlled. The most commonly used control technique has been the typical PWM. However, it is possible to generate a control scheme by FPGA technology. So, the control signals are established by the designer. This kind of control has been called patron control signals. In this paper, a complete mathematical analysis of the output voltage behavior for a 2/spl times/2 SMC, when the time index (/spl beta/) changes, is presented. In addition, simulation results are shown to validate the mathematical analysis.
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