Output Impedance Compensation of a Cascaded Advanced AC-Simulator

Abstract

For testing grid connected components usually an AC power source and external passive components such as inductors and resistors are used. In order to improve the power density of such a system a concept of a cascaded advanced AC-simulator with virtual output impedance has been proposed. Such a system consists of a large signal and a small signal inverter, which are connected in series to emulate arbitrary grid characteristics, like voltage dips, frequency profiles, harmonics and grid impedance. This concept shows some advantages in terms of small signal bandwidth and measurement accuracy. While the large signal inverter merely has to provide the fundamental voltages, the small signal inverter emulates the voltage drop of the virtual impedance as well as harmonics with higher dynamic. Since the expected output voltage of the small signal inverter is much lower compared to the fundamental signals, fast switching MOSFETs with lower Drain-Source voltage can be implemented. However, for small virtual impedance values the output impedance of the large signal generator cannot be neglected and has to considered or compensated. One approach is to compensate the output impedance of the large signal inverter within the control system of the small signal inverter. The implementation and verification of such a compensation concept for a cascaded AC-Simulator with virtual output impedance is presented in this work.