Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage Regulators

Abstract

Output impedance as a function of frequency is discussed in the paper as an important figure of merit for embedded linear voltage regulators. It is shown that output impedance curve of linear voltage regulators is a good indicator of the transient performance to output load current and should be used along with other figure of merits to assess the performance of linear voltage regulators. Output impedance curves of off-chip capacitor based PMOS linear voltage regulator, fully on-chip capacitor-less PMOS linear voltage regulator and open loop NMOS linear voltage regulator are discussed and compared. Output impedance curve is shown to reflect the effects on regulator performance of such parameters as off-chip and on-chip output capacitances, bond-wire parasitic such as inductance and resistance and choice of pass transistor. Phenomenon such as power grid resonance, SSN (Simultaneous Switching Noise) and IR drop are also analyzed using output impedance curve.