Outline of Gmicro/200 and Memory Management Mechanism

Abstract

This paper outlines the 32-bit microprocessor Gmicro/200 and its memory management mechanism on chip. This microprocessor’s target performance is 6 MIPS. To achieve this performance, a 6-stage pipeline, 5-unit distributed processing, 1-kbyte instruction cache, 128-byte stack cache, and 16-byte branch prediction table are used. The virtual memory management mechanism defined by the memory management unit (MMU) is 2-level paging with dual regions. the translation look-aside buffer (TLB) has 32 entries. It translates logical address within one machine cycle (50 ns) to physical address. The pipeline of the address translation and the external bus access cancels address translation delay.