Oscillation ring testing methodology of TSVs in 3D stacked ICs

Abstract

This paper presents on-chip self-testing circuits to detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ring-based oscillator test structure is proposed and simulated based on a high performance fully tunable electrical circuit pi-model where a single and coupled TSVs with ground-signal-ground (GSG) and ground-signal-signal-ground (GSSG) 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. Simulation results are presented using the Keysight/Agilent Advance Design System (ADS) and a standard 0.25 μm CMOS process.