Abstract
ABSTRACTThe electron traps in Si-implanted active layers(n∼1017 cm−3) have been studied by capacitance and conductance DLTS techniques in conjunction with different anneal conditions, which include rapid thermal anneals at different temperatures and furnace anneals with a Si3N4 cap or capless in an AsH3 atmosphere. As compared to the electron traps in as-grown bulk n-GaAs (n∼4×1016 cm−3), nearly the same electron traps, i.e. EL2, EL3, ELM, EL5, EL6 and EL9 can be observed in the Si-implanted layers. Through a comparison with the annealing behavior of the main elect ron traps in bulk n-GaAs, the processing associated origins of some of the traps(EL2, EL3, EL4, EL5 and EL9) observed in Si-implanted GaAs layers have been determined. For some Si-implanted GaAs capped with Si3N4 and furnace annealed, traps EL3 and EMA dominate the trap EL2. In such layers it is found that emission due to EL3 is reduced while emission from EL12 is augmented by increasing the filling pulse width from 10 μs to 5×103 μs. This phenomenon can be explained in terms of a defect reaction enhanced by electron capture, showing a metastability or bistability.
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