Abstract

The structural realization of the PLD-based of a Xilinx type FPGA 32-bit modules of addition with a floating point appropriate to the standard IEEE-754, executed by using the behavioral description of algorithm by language VHDL is offered. The check of functioning of the modules of addition by a method of modeling in system ModelSim Xilinx Edition - MXEII with the help of the verifying stand is realized

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