Abstract
This paper describes a Chip Scale Package (CSP) development project and evaluation of the corresponding organic laminate material. Chip scale packaging can combine the strengths of various packaging technologies, such as the large size and performance advantages of a bare die assembly and the reliability of encapsulated devices. Optimizing the laminate carrier material for low CTE reduces the dimensional mis-match between chip and laminate during Bond and Assembly (BA) and mitigates Chip-Package Interactions (CPI) related fails. Utilizing a low CTE material significantly reduces the strain in the solder joints during the reflow process. Modeling laminate CSP groundrules with the organic material parameters provides stress and strain predictions and highlights parameter ranges for successful BA process capability. Predicted global and chip-site warp data from thermo-mechanical modeling are compared to the measured warpage data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated. Electrical and mechanical tests carried out on the low CTE laminate material and subsequently on the related CSP are described. Recommendations for future CSP development and testing are presented.
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