Order-lot pegging heuristics for minimizing total tardiness in a semiconductor wafer fabrication facility

Abstract

We consider a problem of order-lot pegging in a semiconductor wafer fabrication facility. In the problem, we determine assignments of wafers in lots to orders and plans for input release of wafers into wafer fabrication facility with the objective of minimizing the total tardiness of orders over finite time horizon. The problem is formulated as a mixed integer linear program. To tackle industrial-sized problems, we develop six heuristic algorithms based on the earliest due date rule. The test results on randomly generated problems show that the suggested algorithms give better solutions than an optimization method of a commercial software package within a reasonable computation time.