Abstract
Modern FPGA accelerators can be equipped with many high-bandwidth network I/Os, e.g., 64 x 50 Gbps, enabled by onboard optics or co-packaged optics. Some dozens of tightly coupled FPGA accelerators form an emerging computing platform for distributed data processing. However, a conventional indirect packet network using Ethernet's Intellectual Properties imposes an unacceptably large amount of the logic for handling such high-bandwidth interconnects on an FPGA. Besides the indirect network, another approach builds a direct packet network. Existing direct inter-FPGA networks have a low-radix network topology, e.g., 2-D torus. However, the low-radix network has the disadvantage of a large diameter and large average shortest path length that increases the latency of collectives. To mitigate both problems, we propose a lightweight, fully connected inter-FPGA network called OPTWEB for efficient collectives. Since all end-to-end separate communication paths are statically established using onboard optics, raw block data can be transferred with simple link-level synchronization. Once each source FPGA assigns a communication stream to a path by its internal switch logic between memory-mapped and stream interfaces for remote direct memory access (RDMA), a one-hop transfer is provided. Since each FPGA performs input/output of the remote memory access between all FPGAs simultaneously, multiple RDMAs efficiently form collectives. The OPTWEB network provides 0.71-ÎĽsec start-up latency of collectives among multiple Intel Stratix 10 MX FPGA cards with onboard optics. The OPTWEB network consumes 31.4 and 57.7 percent of adaptive logic modules for aggregate 400-Gbps and 800-Gbps interconnects on a custom Stratix 10 MX 2100 FPGA, respectively. The OPTWEB network reduces by 40 percent the cost compared to a conventional packet network.
Highlights
Parallel data processing using multiple field- cant, the inter-FPGA communication start-up latency typprogrammable gate array (FPGA) accelerators with ically reaches tens of sec order even on a small traditionhigh-bandwidth memory, e.g., HBM2, and high- al system [29], [30].bandwidth network, becomes a way to compute emerg-Direct interconnection networks are attempted on ing parallel applications including deep neural networks an FPGA-accelerator system, e.g., Project Catapult v1 [6],[1] or columnar database [2]
In Japan, we have developed onboard optics using Optical I/O Core for 100-Gbps transceiver (4Ă—25 Gbps), and we have integrated these optics into a custom Intel Stratix 10 FPGA card [19]
In the prototype accelerator system, four ports are used for four FPGAs
Summary
Parallel data processing using multiple field- cant, the inter-FPGA communication start-up latency typprogrammable gate array (FPGA) accelerators with ically reaches tens of sec order even on a small traditionhigh-bandwidth memory, e.g., HBM2, and high- al system [29], [30].bandwidth network, becomes a way to compute emerg-Direct interconnection networks are attempted on ing parallel applications including deep neural networks an FPGA-accelerator system, e.g., Project Catapult v1 [6],[1] or columnar database [2]. Parallel data processing using multiple field- cant, the inter-FPGA communication start-up latency typprogrammable gate array (FPGA) accelerators with ically reaches tens of sec order even on a small traditionhigh-bandwidth memory, e.g., HBM2, and high- al system [29], [30]. Throughput data processing, e.g., sorting operation [3], [4], some FPGA cards have network ports for [5]. In current Ethernet switches, electric SERDES conversion consumes significant power, and the broad area of the aggregate I/O pluggable ports increases the onboard wire length. To mitigate both problems, the optical technology should be tightly coupled with a switch ASIC. Onboard optics are needed to support up to 40 Tbps switch ASIC [22], and CPO commercially becomes mature before 51.2-Tbps switch ASIC is deployed
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