Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect

Abstract

A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads. This expression is based on the alpha power law for deep submicrometer technologies. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 30% for present on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase, which is expected to have a profound effect on traditional design methodologies. The closed form CMOS delay model is applied to the problem of repeater insertion in RLC interconnect. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. It is shown that large errors in the repeater design process are encountered if inductance is neglected. Errors up to 30% can occur if repeaters are inserted without considering the effects of inductance. The error between the RC and RLC models increases as the gate parasitic impedances decrease. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.